Networks enable computers and other devices to communicate. For example, networks can carry data representing video, audio, e-mail, and so forth. Typically, data sent across a network is divided into smaller messages known as packets. By analogy, a packet is much like an envelope you drop in a mailbox. A packet typically includes “payload” and a “header”. The packet's “payload” is analogous to the letter inside the envelope. The packet's “header” is much like the information written on the envelope itself. The header can include information to help network devices handle the packet appropriately. For example, the header can include an address that identifies the packet's destination.
A given packet may “hop” across many different intermediate network forwarding devices (e.g., “routers”, “bridges” and/or “switches”) before reaching its destination. These intermediate devices often perform a variety of packet processing operations. For example, intermediate devices often perform packet classification to determine how to forward a packet further toward its destination or to determine the quality of service to provide.
These intermediate devices are carefully designed to keep apace the increasing volume of traffic traveling across networks. Some architectures implement packet processing using “hardwired” logic such as Application Specific Integrated Circuits (ASICs). While ASICs can operate at high speeds, changing ASIC operation, for example, to adapt to a change in a network protocol can prove difficult.
Other architectures use programmable devices known as network processors. Network processors enable software programmers to quickly reprogram network processor operations. Some network processors feature multiple processing cores to amass packet processing computational power. These cores may operate on packets in parallel. For instance, while one core determines how to forward one packet further toward its destination, a different core determines how to forward another. This enables the network processors to achieve speeds rivaling ASICs while remaining programmable.